Advent of Code 2024 Day 24 (BaseA Style)

[AlteryxCommunityTeam]

Discussion thread for day 24 of the Advent of Code - https://adventofcode.com/2024/day/24

[mmontgomery]

Day 24. More in spoiler

Spoiler

P1: Straight forward iterative macro to get the result. I was hoping for a quick day, but alas, it was not
P2: This took a long time to figure out. I ended up breaking the data into four categories that had out-of-place keys instead of trying to brute force or find the sums:
a. Ends With Z and doesn't contain XOR (this is needed for flexibility). These Z records are out of place
b. Starts with X or Y with XOR operation feeding into key result has to lead to 'AND' or 'XOR'. If this rule isn't met, they are out of place
c. Doesn't End in Z, Isn't Fed by X or Y, and ends in XOR. These second wave keys need to be AND/OR. If the rules aren't met they are out of place
d. Starts with X or Y with AND operation and doesn't feed into second-wave OR. Keys not meeting this rule are out of place

These four rules got me the eight keys out of place. I did it parts then took breaks and came back

[ntakeda]

I will only post PART 2.

The workflow for PART 1 was lost while I was working on PART 2...

Spoiler

My workflow does not automatically replace wires.
I have manually replaced them 4 times.

Part2.
As the problem statement says, this is a logic circuit (adder).
My graduate major was semiconductor devices, but it is difficult to understand how this works.
So, I used Alteryx and "Pen and Paper" to figure out how the circuit works.
Then we can see that the circuit looks like the macro image.

x00 XOR y00 -> z00
x00 AND y00 -> AA
x01 XOR y01 -> BB
AA XOR BB -> z01
AA AND BB -> CC
x01 and y01 -> DD
CC AND DD -> EE
It goes on like this...(It's hard to explain.)

I made this into a workflow and identified four places where the workflow stopped.

  

[gawa]

It reminds me of 2023D25. 

Without looking at Network(Graph) structure, I could not make it. Just curiosity, how can we solve this puzzle with the generalized WF that accepts any input data?

[DaisukeTsuchiya]

P2 was difficult.

Spoiler

For P1, all output parameter was set as the main flow within the iterative macro. In each loop, the unknown parameters were determined step by step.

P2 was particularly challenging. Following the advice of my colleague, @Tokimatsu , Network Visualization Tool was used to identify problematic patterns visually. Among the four swapped pairs, three were easy to find because the output to z was not from XOR. For the last pair, I searched for inputs to z that were from neither XOR nor OR. This required a visual check and validated by adding the binary numbers from X and Y resulted in Z.

The Network Visualization Tool can visually highlight problems. Differentiating using direction, color, and size made the process much clearer. Additionally, thanks to @Tokimatsu's advice, gate names are included in the labels, which significantly improved clarity.

[AkimasaKajitani]

Solved!

Spoiler

My approach is fixing by hand supported by Designer.


Part 1



In Part 2, in order to understand what was wrong, I used a batch macro to input 1s one bit at a time from the bottom and observed how the output changed.
This helped me to figure out where was wrong.


This means z4,5,10,11,22,23,37 are something wrong!

I also thought there should be something wrong with the internal wires, so I checked the bits of all of the wires as well.



This gave me a rough idea of ​​what was wrong, and I was able to identify what was wrong and manually find the answer.

Part 2



Part 2 macro

[Hub119]

Part 1 here was fairly quick and easy... Part 2 was a BEAST!  This involved lots of research into circuit adders to better understand how things SHOULD be working.  I built out a test macro to check for the first break point where a problem existed and therefore wires were "crossed" in that area that needed swapping.  Shout out to @DaisukeTsuchiya for the hint of using the Network Analysis tool to better visualize what was going on.  Using my "next error" check macro along with this viz, and updating pairs one at a time until the circuit produced the proper output allowed me to quickly identify and sort out the circuit.

Spoiler

Workflow

Spoiler

P1 Macro

Spoiler

P2 Error Check Macro

Spoiler

Circuit Network Viz

[CoG]

Part 1 was relatively easy. An iterative macro is perfect for evaluating all logic. Part 2, as others have said, is very easy to make very difficult. I knew the general vicinity of all errored outputs within an hour, then proceeded to take the next day trying to wrap my head around finding the specific answer. Knowing how circuits work with boolean logic will be a tremendous asset although I still struggled to build with Alteryx. This was a very manual problem for me.

Spoiler

My mess of a workflow with very little structure. Two tips I will provide: Try checking simple additions, all bits = 0 except for one for example. Next, try to build a macro/workflow that categorizes each step by which input bits it handles (basically Network Analysis mentioned above). Lastly look for patterns that are required for adders (e.g. output bits are the result of XOR operation, with the exception of most significant/last output bit, since that last bit is just the carry from second to last calculation).

[Tokimatsu]

At first I answered Part2 by looking at the network diagram. After that, I created a workflow to derive the answer to part 2 from the relationship between the operators. However, other people's data may not give the correct answer.

Spoiler

I checked following combination. At first check x,y,z relation because that related to digit number. then following it.

X(n) AND Y(n) = AND1(n)
X(n) XOR Y(n) = XOR1(n)

OR(n-1) XOR XOR1(n) = XOR2(n) = Z(n)
OR(n-1) AND XOR1(n) = AND2(n)

AND1(n) OR AND2(n) = OR(n)